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|class="MainPageBG" style="width:55%;border:1px solid #cef2e0;background-color:#f5fffa;vertical-align:top;color:#000"| | |class="MainPageBG" style="width:55%;border:1px solid #cef2e0;background-color:#f5fffa;vertical-align:top;color:#000"| | ||
{|width="100%" cellpadding="2" cellspacing="5" style="vertical-align:top;background-color:#f5fffa" | {|width="100%" cellpadding="2" cellspacing="5" style="vertical-align:top;background-color:#f5fffa" | ||
! <h2 style="margin:0;background-color:#cef2e0;font-size:120%;font-weight:bold;border:1px solid #a3bfb1;text-align:left;color:#000;padding:0.2em 0.4em;"> Scope | ! <h2 style="margin:0;background-color:#cef2e0;font-size:120%;font-weight:bold;border:1px solid #a3bfb1;text-align:left;color:#000;padding:0.2em 0.4em;"> Scope</h2> | ||
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|style="color:#000"|[[Image:ee_ti.jpg|left|400px]] The first-generation spintronic devices use the exchange interaction between conduction electron spins and local spins in magnetic materials to create spin-polarized currents or to manipulate nanomagnets by spin transfer from spin-polarized currents. One of the burgeoning areas of next-generation spintronics exploits relativistic effects in nonmagnetic materials know as spin-orbit coupling (SOC) to generate, detect or exploit spin-polarized currents. In particular, strong surface and bulk SOC effects can be introduced into heterostructures using recently discovered topological insulator (TI) materials. They possess a usual band gap in the bulk while also hosting metallic surfaces whose low-energy quasiparticles behave as massless Dirac fermions with spins locked to their momenta. The SOC can also give rise to strong Dzyaloshinskii-Moriya interaction (DMI) which competes with conventional exchange interaction to create chiral domain walls or skyrmions as swirling spin textures characterized by nanoscale size, topological stability against defects and impurities, and gyro-dynamics analogous to that of a charged particle under magnetic field. In this workshop, we bring together experimentalists and theorists to review the current status of phenomena topology of skyrmions in real space or topology of Dirac electrons in ''k''-space, as well as their interplay, can be exploited for novel ultralow power memory and logic device, which can potentially help to solve the heating and scaling issues associated with the convetional CMOS technology. | |style="color:#000"|[[Image:ee_ti.jpg|left|400px]] The first-generation spintronic devices use the exchange interaction between conduction electron spins and local spins in magnetic materials to create spin-polarized currents or to manipulate nanomagnets by spin transfer from spin-polarized currents. One of the burgeoning areas of next-generation spintronics exploits relativistic effects in nonmagnetic materials know as spin-orbit coupling (SOC) to generate, detect or exploit spin-polarized currents. In particular, strong surface and bulk SOC effects can be introduced into heterostructures using recently discovered topological insulator (TI) materials. They possess a usual band gap in the bulk while also hosting metallic surfaces whose low-energy quasiparticles behave as massless Dirac fermions with spins locked to their momenta. The SOC can also give rise to strong Dzyaloshinskii-Moriya interaction (DMI) which competes with conventional exchange interaction to create chiral domain walls or skyrmions as swirling spin textures characterized by nanoscale size, topological stability against defects and impurities, and gyro-dynamics analogous to that of a charged particle under magnetic field. | ||
! <h2 style="margin:0;background-color:#cef2e0;font-size:120%;font-weight:bold;border:1px solid #a3bfb1;text-align:left;color:#000;padding:0.2em 0.4em;">Objectives</h2> | |||
In this workshop, we bring together experimentalists and theorists to review the current status of phenomena topology of skyrmions in real space or topology of Dirac electrons in ''k''-space, as well as their interplay, can be exploited for novel ultralow power memory and logic device, which can potentially help to solve the heating and scaling issues associated with the convetional CMOS technology. | |||
'''Invited Speakers:''' | '''Invited Speakers:''' |
Revision as of 12:57, 13 May 2015
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